1. Field of the Invention
This invention is related to processors and, more particularly, to time stamp counters in processors.
2. Description of the Related Art
Processor instruction set architectures (ISAs) often specify a time stamp counter (TSC) to provide for the calculation of time in the computer system. Generally, the time stamp counter can be any architected resource that is defined to increment at some interval, so that time can be determined (or at least estimated) based on the value in the time stamp counter. For example, the x86 processor ISA (also referred to as the Intel Architecture (IA)-32 ISA, and includes various extensions such as the AMD-64 extensions defined by Advanced Micro Devices, Inc.) includes a TSC model specific register (MSR) that stores the TSC value. Instructions are provided to read and write the time stamp counter. Other instruction set architectures may define similar time measurement facilities (e.g. the PowerPC real time clock register).
In the case of the TSC MSR in the x86 processor ISA, the original definition of the TSC was to increment each processor clock cycle. With knowledge of the clock frequency of the processor, software could use the value in the TSC MSR to determine how much actual time had elapsed during an operation, keep track of the actual time for time/date purposes, etc. The actual time is also often referred to as “wall clock” time, to distinguish from time measured in clock cycle counts or other intervals. While this definition of the TSC MSR was useful when processor clock frequencies were constant for a given processor instance, the advent of aggressive power management techniques which vary the processor clock frequency made this definition unworkable because increments of the TSC MSR no longer represented equal amounts of time. Similarly, in a multiprocessor system (or multicore chip multiprocessors (CMPs)), the TSC in different processors could measure significantly different numbers of clock cycles if the processors were power-managed independently. Even if the processors were power-managed together, smaller differences in clock cycle measurements could occur as processors enter and leave various power states at slightly different times.
Accordingly, later versions of the processors implemented the TSC MSR in the north bridge used to bridge between the processor interface to the memory and various peripheral interfaces such as the peripheral component interconnect (PCI), the advanced graphics port (AGP), etc. Since the north bridge clock frequency is not normally varied, the TSC MSR being incremented at the north bridge clock frequency provides for more reliable time measurement. However, the latency to read the TSC MSR increases substantially.